1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device that stores information in floating gates.
2. Description of the Related Art
A nonvolatile semiconductor memory stores information by the presence or absence of charge accumulated on floating gates. Examples of such a nonvolatile semiconductor memory include a flash memory, which erases information in memory cells simultaneously. FIG. 24 shows the configuration of a conventional flash memory array. In FIG. 24, reference numeral 1 is a nonvolatile memory cell including a floating gate and a control gate, 2 is a word line connected to the control gate of the nonvolatile memory cell 1, 3 is a bit line, and 4 is a source line. As shown in FIG. 24, each nonvolatile memory cell 1 is formed independently at the intersection of the word line 2 and the bit line 3.
To erase data from the nonvolatile memory cells 1, a high voltage is applied to the word lines 2 and the source lines 4. At the time of erasing, the same voltage VNEG is applied to all the word lines via switching elements 5 selected by an erasing block decoder 6. For reading and writing, each of the nonvolatile memory cells is selected independently by a selecting circuit (not shown in FIG. 24). Like the word lines 2, the same voltage VPOS is applied simultaneously to the source lines 4 during erasing. In other words, data is erased at once during erasing.
The nonvolatile memory includes a redundant memory cell array 8, which is located adjacent to a normal memory cell array 7, to repair memory defects in a redundant manner. The normal memory cell array 7 and the redundant memory cell array 8 share the bit lines 3. When a redundant word line 2R is used, the word line having a defective bit is not used.
However, an erasing voltage is applied to the cells connected to the defective word line because the erasing circuit is the same. Consequently, those cells are over-erased, compared with the cells connected to other normal word lines 2. Thus, the memory cells connected to the defective word line are depleted to cause bit-line leakage during reading, resulting in malfunction.
To solve the problem, e.g., JP 7(1995)-230700 A discloses a method for preventing the application of an erasing bias to the source line of a replaced defective cell. Using this method, however, the erasing bias is applied to the word line. Therefore, charge is drawn from the floating gate, which may cause over-erasing.
There is another method in which a redundant word line is provided or each erasing block, as shown in FIG. 25. For example, when a second formal erasing block 72 is found to be defective, it is replaced by a redundant erasing block 8, as shown in FIG. 25. Since the second normal erasing block 72 is not accessed permanently, no erasing bias is applied thereto. Therefore, such over-erasing as described above does not occur.
However, the erasing block is usually composed of tens to hundreds of kilobits as a unit, and the size of a unit to be replaced for one defective cell is the same as that of the erasing block. Thus, the repair efficiency is rather poor.
Therefore, with the foregoing in mind, it is an object of the present invention to provide a nonvolatile semiconductor memory device that can prevent over-erasing even if a memory cell is replaced in the word line direction and provide high repair efficiency.
To achieve the above object, a first nonvolatile semiconductor memory device of the present invention includes: N (N is a natural number) normal memory cell arrays, a redundant memory cell array, (N+1) erasing bias circuits, N erasing decode circuits, and N redundancy control circuits. Each of the N normal memory cell arrays includes the arrangement of two or more nonvolatile memory cells, each having a control gate and a floating gate. The redundant memory cell array includes the arrangement of two or more nonvolatile memory cells, each having the same configuration as that of the nonvolatile memory cell in the normal memory cell array. The (N+1) erasing bias circuits apply an erasing bias for erasing data stored in the N normal memory cell. arrays and the redundant memory cell array. The N erasing decode circuits decode defective address information. The N redundancy control circuits are connected in series so that a preceding stage controls the next in order to store the defective address information for switching the (N+1) erasing bias circuits based on the defective address information responsive to output signals from the respective N erasing decode circuits. The (N+1) erasing bias circuits inhibit application of the erasing bias to word and source lines connected to the control gates of any one of the N normal memory cell arrays that is replaced by the redundant memory cell array and also inhibit application of the erasing bias to word and source lines connected to the control gates of the unused redundant memory cell array under a switching operation by the N redundancy control circuits in erasing data.
In the first nonvolatile semiconductor memory device, it is preferable that the size of an array of the N normal memory cell arrays is the same as that of the redundant memory cell array and is equal to or less than that of a minimum erasing block.
In the first nonvolatile semiconductor memory device, it is preferable that the (N+1) erasing bias circuits apply the erasing bias to any number of memory cell arrays among the N normal memory cell arrays and the redundant memory cell array under a switching operation by the N redundancy control circuits based on output signals from the N erasing decode circuits.
In the first nonvolatile semiconductor memory device, it is preferable that each of the N redundancy control circuits includes an input terminal, a first output terminal, and a second output terminal. The input terminal receives an output signal from the erasing decode circuit and a defective address program activation signal. The first output terminal switches an erasing bias activation signal and outputs it to one of the adjacent erasing bias circuits, and the second output terminal switches the erasing bias activation signal and outputs it to the other erasing bias circuit. It is also preferable that the second output terminal of one of the adjacent redundancy control circuits and the first output terminal of the other redundancy control circuit are connected in common. Each of the N redundancy control circuits stores the defective address information based on the output signal from the erasing decode circuit when the defective address program activation signal is activated, and among the N redundancy control circuits, a redundancy control circuit storing the defective address information controls the next redundancy control circuit so as to switch the terminals for outputting the erasing bias activation signal.
The above configuration can eliminate over-erased memory cells because no erasing bias is applied to the unused word and source lines of a memory cell array. Therefore, it can prevent malfunction due to bit-line leakage. Moreover, this configuration enables the replacement of a normal memory cell array by a redundant memory cell array for each word line, thus providing a higher repair efficiency than that of a conventional replacement for each erasing block.
In the first nonvolatile semiconductor memory device, it is preferable that each of the N redundancy control circuits includes a nonvolatile memory cell having a control gate and a floating gate to store the defective address information.
In such a case, it is preferable that each of the N redundancy control circuits includes the following: a nonvolatile memory cell having a gate connected to the preceding redundancy control circuit, a source connected to a first power line, and a drain connected to a common node; a first PMOS transistor having a gate connected to the gate of the nonvolatile memory cell, a source connected to a second power line, and a drain connected to the common node; a second PMOS transistor having a gate connected to the next redundancy control circuit, a source connected to the second power line, and a drain connected to the common node; an inverter having an input terminal connected to the common node and an output terminal connected to the gate of the second PMOS transistor; a first NMOS transistor having a gate receiving the defective address program activation signal, a drain connected to the common node, and a source receiving the defective address information from the erasing decode circuit; a second NMOS transistor having a gate connected to the output terminal of the inverter, a source acting as the first output terminal for switching the erasing bias activation signal to be output, and a drain connected to the source of the first NMOS transistor; and a third NMOS transistor having a gate connected to the input terminal of the inverter, a source acting as the second output terminal for switching the erasing bias activation signal to be output, and a drain connected to the source of the first NMOS transistor.
According to this configuration, defective address information is stored in the redundancy control circuit via an erasing decode signal. Therefore, only the defective address program activation signal FAPEN is used as a redundancy control signal. Thus, many signals for redundancy decoding are not necessary, which enables the replacement for each word line with a simple layout.
Alternatively, in the first nonvolatile semiconductor memory device, it is preferable that each of the N redundancy control circuits includes a static memory cell having two inverters to store the defective address information.
In such a case, it is preferable that each of the N redundancy control circuits includes the following: a static memory cell having first and second inverters, where an input terminal of the first inverter is connected to an output terminal of the second inverter, while an output terminal of the first inverter is connected to an input terminal of the second inverter; a first NMOS transistor having a gate receiving the defective address program activation signal, a drain connected to one input/output terminal of the static memory cell, and a source receiving the defective address information from the erasing decode circuit; a second NMOS transistor having a gate connected to the other input/output terminal of the static memory cell and a source connected to a first power line; a third NMOS transistor having a gate connected to the preceding redundancy control circuit, a drain connected to a common node, and a source connected to the drain of the second NMOS transistor; a first PMOS transistor having a gate connected to the gate of the third NMOS transistor, a drain connected to the common node, and a source connected to a second power line; a second PMOS transistor having a gate connected to the next redundancy control circuit, a source connected to the second power line, and a drain connected to the common node; a third inverter having an input terminal connected to the common node and an output terminal connected to the gate of the second PMOS transistor; a fourth NMOS transistor having a gate connected to the output terminal of the third inverter, a source acting as the first output terminal for switching the erasing bias activation signal to be output, and a drain connected to the source of the first NMOS transistor; and a fifth NMOS transistor having a gate connected to the input terminal of the third inverter, a source acting as the second output terminal for switching the erasing bias activation signal to be output, and a drain connected to the source of the first NMOS transistor.
This configuration employs the static memory cell to store defective address information. Therefore, it is not necessary to apply a high voltage, which eliminates the need for a device with a high withstand voltage. Thus, a large separation width, longer channel length, channel offset, and the like are not required to maintain a withstand voltage, simplifying the layout.
To achieve the above object, a second nonvolatile semiconductor memory device of the present invention includes an erasing pre-decode circuit and erasing decode circuits: the erasing pre-decode circuit receives a plurality of erasing address signals and outputs a plurality of first and second erasing pre-decode signals; the erasing decode circuits receive the first and second erasing pre-decode signals and output a plurality of erasing decode signals. Any combination of the erasing address signals activates the desired number of erasing pre-decode signals of the first and second erasing pre-decode signals so that the desired number of erasing decode signals are activated.
This configuration can set the size of a block to be erased in a nonvolatile memory array flexibly with the same erasing decode circuit. Thus, modification of the erasing circuit can be made easily in accordance with the use of a memory chip.
In the second nonvolatile semiconductor memory device, it is preferable that the erasing pre-decode circuit includes an address degeneration circuit and a multiplex pre-decode circuit: the address degeneration circuit receives the erasing address signals and outputs the same number of address degeneration signals as that of the erasing address signals; the multiplex pre-decode circuit receives the erasing address signals and the address degeneration signals and outputs the erasing pre-decode signals. A combination of the erasing address signals generates any address degeneration signal so as to degenerate any address of the erasing address signals and thus any of the erasing pre-decode signals are multiplexed.
This configuration provides the address degeneration circuit and the multiplex pre-decode circuit separately. Therefore, the erasing pre-decode signals can be combined for multiplexing with the same erasing pre-decode circuit and only by modifying the contents of the address degeneration circuit. Thus, modification of the erasing circuit can be made easily in accordance with the use of a memory chip.
In such a case, it is preferable that the address degeneration circuit includes a decoder and a group of combinatorial logic elements: the decoder receives the erasing address signals; the group of combinatorial logic elements receives all outputs from the decoder and outputs the address degeneration signals. It is also preferable that the group of combinatorial logic elements includes OR circuits, each receiving the same number of control signals as that of the erasing address signals and outputting the address degeneration signal in accordance with a combination of the erasing address signals and the control signals. Moreover, it is preferable that the control signals are stored in an information storage means located separately from the address degeneration circuit on the same substrate.
This configuration can change the combinations for address degeneration by changing the states of the control signals in the same chip. Thus, the size of a block to be erased can be changed in the same chip, allowing the device to be used for many applications.
In the second nonvolatile semiconductor memory device, it is preferable that the group of combinatorial logic elements includes OR circuits, each including the same number of nonvolatile memory cells as that of the erasing address signals; control gates of the nonvolatile memory cells are each supplied with the erasing address signal and drains thereof are connected in common to form an output node of the OR circuit; and the OR circuit outputs the address degeneration signal in accordance with a combination of the erasing address signals and information stored in the nonvolatile memory cells. In such a case, it is preferable that desired information is stored in the nonvolatile memory cells by supplying the erasing address signals to each of the control gates of the nonvolatile memory cells and applying a desired voltage to the output node of the OR circuit.
This configuration can change the combinations for address degeneration by modifying the contents of the nonvolatile memory cells in the address degeneration circuit in the same chip. Thus, the size of a block to be erased can be changed in the same chip, allowing the device to be used for many applications. Moreover, the number of excess control signal lines can be reduced, so that a smaller layout area can be achieved.
It is preferable that the first nonvolatile semiconductor memory device further includes an erasing pre-decode circuit including an address degeneration circuit and a multiplex pre-decode circuit: the address degeneration circuit receives a plurality of erasing address signals and outputs the same number of address degeneration signals as that of the erasing address signals; the multiplex pre-decode circuit receives the erasing address signals and the address degeneration signals and outputs a plurality of first and second erasing pre-decode signals. It is also preferable that the erasing decode circuits receive the first and second erasing pre-decode signals from the erasing pre-decode circuit and output erasing decode signals, with which any number of normal memory cell arrays in a plurality of combinations are activated so as to repair a defective address of any one of those normal memory cell arrays. In such a case, it is preferable that the erasing decode circuits are shared in an erasing mode and a program mode, and the number of source lines to be selected in the program mode is made smaller than that in the erasing mode by changing the activated address degeneration signals depending on the erasing and program modes.
According to this configuration, the number of source lines to which a bias is applied in the program mode can be made smaller than that in the erasing mode. Thus, source-line disturbance can be reduced, thereby ensuring high reliability.